Industry · Photonics
Photonics & optical devices
A photonic integrated circuit lives or dies at its interfaces: how light couples from fiber to chip, whether the package can hold nanometer alignment, and whether a design that simulates beautifully still performs once it is fabricated. Agentriq designs optical devices to be low-loss and manufacturable at once, then verifies every result in the loop.
01The problem
NVIDIA is scaling co-packaged optics, its Spectrum-X and Quantum-X Photonics switches, to move light directly into the switch silicon of AI clusters; NVIDIA reports that this co-packaged design uses about four times fewer lasers, three and a half times better power efficiency and sixty three times better signal integrity than conventional pluggable optics. Across silicon photonics the hard part is rarely the waveguide, it is the interface: fiber-to-chip coupling has to be held to nanometers, packaging can exceed 80% of a PIC's cost and testing as much as a further 29%, and every decibel of insertion loss you chase tends to make the device harder to yield.
02How we solve it
Optimize for loss and manufacturability at once.
We drive fabrication-aware inverse design so the geometry that minimizes insertion loss is also the one the foundry can actually print.
Adjoint-method inverse design
Compute the gradient over thousands of geometry parameters from only two simulations per iteration, one forward and one adjoint, so free-form devices converge in a fraction of the solver calls.
Fabrication-aware, yield-optimized design
Fold DUV and e-beam lithography models into the optimization so the design corrects for process bias up front; published fabrication-aware work reports up to 0.6 dB lower insertion loss per device.
Neural and surrogate-accelerated inverse design
Train surrogate and neural models on solver data to predict device response near-instantly, steering the search toward promising geometries before spending full-wave simulations.
Multi-scale FDTD and FEM to circuit
Simulate components with full-wave FDTD and FEM, distill them into compact models, and validate the whole PIC at circuit level so component gains hold at system scale.
03What it produces
Low-loss, compact, manufacturable by design.
Devices that hold their insertion-loss budget in silicon and not just in simulation, with fabrication-aware inverse design demonstrating up to 0.6 dB lower loss on real fabricated components and free-form geometries reaching footprints of tens of square microns.
04The agentic loop
From layout to a verified device.
Agentriq runs the whole cycle as a closed agent loop: propose a geometry, simulate it under fabrication-aware models, verify it against loss and design-rule targets, diagnose any failure, and write the winning design and its evidence back to the PDK.
- 01Generate a candidate geometry with adjoint or surrogate-guided inverse design, then simulate it with fabrication-aware full-wave FDTD and FEM plus compact-model circuit checks.
- 02A verification agent re-checks insertion loss, bandwidth and foundry design rules against spec, across process corners.
- 03On a miss, a root-cause agent with Agentic RAG traces the failure to geometry, lithography bias or coupling, drawing on PDK documents and prior runs.
- 04A judge agent decides iterate, accept or escalate.
- 05The accepted design, its figures of merit and its evidence are written back to the PDK and the project record.
05Tooling
Simulation, solvers & frameworks.
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